Implementation of Dual Modulus Prescaler in True Single Phase Clock (TSPC)
Authors:
Ch.Priyanka,Mr.K.Thirupathi,Mr.M.Devadas
Page No: 204 - 210
Abstract:
A high speed CMOS divideby-16/17 dual modulus prescaler has been designed using 250 nm CMOS technology. It consists of the pseudo divide-by- 2/3 prescaler and an asynchronous divide-by-8 prescaler, which are all implemented in TSPC structure.
Description:
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Volume & Issue
Volume-1,ISSUE-2
Keywords
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