ADOPTION OF SOFT-ERROR-RESIENT SRAM IN WITH PARALLEL TCAM
Authors:
G.Kishore Reddy, P.Sreenivasa Reddy, A.Srinivasulu Reddy, CH.Hanok, N.Kesava Chowdary, P.V.Sairam Naidu
Page No: 706-718
Abstract:
Abstract— For packet classification in software-defined networking (SDN) and OpenFlow applications, ternary content-addressable memory (TCAM) on field-programmable gate arrays (FPGAs) based on static random access memory (SRAM) is utilized. The majority of a TCAM design on FPGAs is made up of SRAMs that implement TCAM contents, which are susceptible to soft mistakes. It is difficult to safeguard SRAM-based TCAMs from soft errors while preserving high search performance and critical path delay. A low-cost, low-response-time method for protecting SRAM-based TCAMs is presented in this brief. This method has a low critical path overhead and detects faults using straightforward, single-bit parity. This method uses the binary-encoded TCAM table that is kept up to date in SRAM-based TCAMs to construct an inexpensive, low-response-time error-correction system. The process of error-correction is carried out in the background, enabling concurrent lookup operations and preserving a high search speed. On a 1024 × 40 size TCAM on Artix-7 FPGA, the suggested method maintains a search pace of 222 million searches per second while offering protection against soft mistakes with a reaction time of 293 ns.
Description:
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Volume & Issue
Volume-14,Issue-4
Keywords
Index Terms— Memory architecture, soft faults, field-programmable gate arrays (FPGA), and ternary content-addressable memory (TCAM) based on static random access memory (SRAM).