DESIGN AND IMPLEMENTATION OF HIGH SPEED 32-BIT VEDIC MULTIPLIER USING VERILOG HDL
Authors:
1Mr. M.V.V. SATYA CHOWDARY, K. SAI KARTHIK REDDY, N. SAIKIRAN, M. PRAVALIKA, M. CHANDRAMOHAN REDDY
Page No: 247-260
Abstract:
The increasing demand for high-speed digital arithmetic operations in modern computing systems necessitates the development of efficient multiplication techniques.
Description:
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Volume & Issue
Volume-14,ISSUE-5
Keywords
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