Abstract:

In digital systems, multiplication is a basic operation that is frequently utilized in embedded systems, machine learning, and digital signal processing (DSP). One of the most widely used architectures for effectively handling signed number multiplication with two's complement representation is the Baugh-Wooley multiplier. This project's main goal is to use the Vivado design tool to create a 16-bit Baugh-Wooley multiplier that uses less power and occupies less space. The design delivers enhanced power and space efficiency without sacrificing accuracy or speed by using improvements such narrowing the hardware architecture, eliminating switching activity, and reducing partial product complexity. With the help of sophisticated tools and focused architectural enhancements, this project demonstrates how the increasing need for small, energy-efficient hardware solutions may be met.

Description:

.