Abstract:

The design of Multiply-Accumulate (MAC) units is an essential component in the area of digital signal processing, since it is responsible for ensuring that high-performance computations are carried out. Applications of the MAC design can be found in a variety of industries, including digital signal processing, communications, and artificial intelligence. In these areas, MAC operations are essential for the efficient computing of convolutional neural networks, digital filters, and other signal processing tasks. At the moment, MAC units typically consist of separate adders and multipliers, which results in an increase in the complexity of the hardware and the amount of power that is consumed. The currently available systems frequently have difficulty finding a happy medium between speed and the utilization of resources. As a result of the independent implementation of adders and multipliers, traditional MAC architectures involve the utilization of redundant hardware. Adders and multipliers that are kept separate from one another contribute to higher power consumption, which in turn limits energy efficiency. As a result of its architecture, the currently available systems could experience difficulties in terms of scalability, particularly when attempting to achieve high-performance computing. This study presents a novel approach to the design of MAC units by utilizing unified adders and multipliers. The objective of this work is to improve both the speed of the system and its consumption of resources. Integrated unified adders and multipliers are incorporated into the suggested technique, which optimizes the MAC unit for increased speed and efficiency improvements. Through the employment of a unified architecture, the design brings about a reduction in power consumption, a reduction in redundancy, and an enhancement of resource utilization.

Description:

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