Abstract:

The architecture of Network-on-Chip (NoC) routers is an essential component in ensuring that data transmission is carried out in an effective manner. This research proposes a novel approach to the design of NoC routers that places an emphasis on the efficiency of the available space. A hybrid method that is specifically designed for NoCs is presented, with the objective of considerably lowering both latency and power consumption. NoC architectures that are now in use often make use of either circuit switching or packet switching approaches, both of which have their own characteristics and limits. Compared to packet switching, which suffers from higher power consumption and congestion, circuit switching can result in high latency due to the significant amount of time required for setup. In order to overcome these limitations, the hybrid scheme that we have presented combines virtual circuit switching with the methods of circuit and packet switching that are already operational. Using our technique, we are able to maximize resource efficiency while simultaneously minimizing latency and throughput. This is accomplished by enabling numerous virtual circuit-switched (VCS) connections to share a single physical channel. As an additional benefit, the use of virtual circuit switching results in the introduction of dynamic routing flexibility, which improves adaptability to different traffic characteristics. Therefore, the results of this work demonstrate that our hybrid system is superior in terms of both performance and efficiency when compared to typical NoC architectures.

Description:

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