DESIGN AND IMPLEMENTATION OF 32-BIT VEDIC MULTIPLIER BASED ON HIERARCHICAL STRUCTURE
Authors:
K. Sambasiva Rao , B. Kruparani , B. Rajesh, B. Navadeep, CH. Raj Shekar
Page No: 29-37
Abstract:
The design and implementation of high-speed arithmetic units is an important requirement in modern digital systems such as signal processing, image processing, and communication applications. Multiplication is one of the most time-consuming operations in digital circuits, and improving the speed of multipliers significantly enhances overall system performance.
Description:
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Volume & Issue
Volume-15,ISSUE-3
Keywords
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